Meta Announces Four New Custom Chips for AI and Recommendation Systems

Meta Platforms Inc. announced Wednesday the development of four new generations of custom-built computer chips. These chips power generative AI features and content ranking systems within its applications. The hardware integrates into Meta‘s existing chip line known as MTIA or Meta Training and Inference Accelerators.

Chip Specifications and Performance Metrics

The MTIA family includes four distinct generations. Each is optimized for specific workload requirements with progressively improving performance metrics.

• MTIA 300: Already in production as of early 2026. It trains algorithms ranking content for hundreds of millions of daily users on Facebook and Instagram. It uses one compute chiplet, two network chiplets, and several high-bandwidth memory stacks. The chip operates at 800 watts TDP with HBM bandwidth of 6.1 TB/s.

• MTIA 400: Currently undergoing lab testing with deployment expected at data centers soon. Meta states this generation delivers performance competitive with leading commercial products. It combines two compute chiplets to double compute density compared to the MTIA 300. The chip supports enhanced versions of MX8 and MX4 low-precision formats for efficient generative AI inference. It operates at 1,200 watts TDP with HBM bandwidth of 9.2 TB/s.

• MTIA 450: Expected to ship in early 2027. This generation doubles the high-bandwidth memory bandwidth from the MTIA 400. Both chips maintain 288 GB HBM capacity. Meta describes its bandwidth as much higher than existing leading commercial products. The chip increases MX4 FLOPS by 75% and introduces hardware acceleration for attention and feed-forward network computation. It operates at 1,400 watts TDP with HBM bandwidth of 18.4 TB/s.

• MTIA 500: Slated for deployment later in 2027. This generation adds approximately 50 percent HBM bandwidth over the MTIA 450, reaching 27.6 TB/s total. It also includes up to 80 percent more HBM capacity at 384-512 GB. The chip utilizes a 2×2 configuration of smaller compute chiplets surrounded by several HBM stacks and two network chiplets. An SoC chiplet handles PCIe connectivity. It operates at 1,700 watts TDP.

According to Meta‘s technical documentation, HBM bandwidth increases 4.5 times from MTIA 300 through MTIA 500. Compute FLOPs increase 25 times across the four generations.

Architecture and Manufacturing Partnerships

The MTIA chips are developed in partnership with Broadcom. They are fabricated by Taiwan Semiconductor Manufacturing Corporation (TSMC). TSMC is the world’s leading chip producer. The semiconductors build on top of the open-source RISC-V architecture. This provides flexibility and cost advantages over proprietary architectures.

Each processing element within the chips contains two RISC-V vector cores. It includes a dot product engine for matrix multiplication operations. Special function units handle activations and elementwise operations. Reduction engines manage accumulation and inter-chiplet communication. DMA engines handle data movement in and out of local scratch memory.

The modular chiplet-based design allows new generations to drop into existing rack system infrastructure. This accelerates time-to-production. All four chips use the same chassis, rack, and network infrastructure. This enables easy interchange between generations. A rack configured with 72 MTIA chips forms a single scale-up domain for Meta‘s data center operations.

Strategic Deployment and Workload Optimization

Meta‘s MTIA strategy rests on three pillars according to company documentation: rapid, iterative development; inference-first focus; and building on industry standards. While the semiconductor industry typically launches new AI chips every one to two years, Meta has developed capacity to release its chips every six months or less. This accelerated pace enables quick adaptation to evolving AI techniques and adoption of latest hardware technologies.

Mainstream chips are typically built for large-scale generative AI pre-training and then applied to other workloads like inference. Meta takes the opposite approach: MTIA 450 and 500 are optimized first for generative AI inference. Then they support other workloads including ranking and recommendations training and inference.

MTIA is built natively on industry-standard software and hardware ecosystems including PyTorch, vLLM, Triton, and the Open Compute Project (OCP). This enables frictionless adoption by developers familiar with these standards. Meta has already deployed hundreds of thousands of MTIA chips across its apps for inference workloads on organic content and advertisements. The company states that this custom full-stack solution achieves greater compute efficiency than general-purpose chips for Meta‘s intended purposes. This makes MTIA more cost-efficient for its specific workloads.

For certain training workloads, particularly large-scale generative AI pre-training, Meta continues to rely on Nvidia GPUs including H100/H200 and B200/B300 models. The company maintains a diverse silicon portfolio while keeping custom MTIA chips at the center of its AI infrastructure strategy for inference-heavy tasks.

Industry Context and Future Roadmap

The chip announcement occurs within Meta‘s broader AI infrastructure strategy. This includes a long-term $100 billion agreement with AMD announced on February 24, 2026. Continued reliance on Nvidia GPUs for certain training workloads persists. Diversification across multiple silicon suppliers reduces dependence on any single vendor. Custom silicon at the center of Meta‘s AI infrastructure strategy leverages best solutions from industry leaders.

Meta‘s approach reflects a common trend among large technology companies developing custom AI hardware. Companies including Google, Amazon, and Microsoft have also developed proprietary chips for their data centers. The competition extends beyond performance to cost-efficiency per inference operation, which becomes critical at scale. The portfolio approach Meta describes allows deployment of various chips optimized for different workloads rather than relying on a single chip type. This mirrors strategies employed by other technology companies that maintain diverse silicon portfolios to meet varying computational demands across their infrastructure.

Meta‘s documentation emphasizes that no single chip can meet all demands across varying needs. The MTIA portfolio addresses ranking and recommendations training (MTIA 300), generative AI inference production (MTIA 450, MTIA 500), additional workloads as needed including ranking and recommendations inference, and generative AI training capabilities.

The chips support low-precision data types such as MX4 and MX8. These reduce computing power requirements for inference without significantly affecting model quality. MX4 on MTIA 450 delivers six times the FLOPs of FP16/BF16 formats with mixed low-precision computation. This avoids software overhead from data type conversion. The infrastructure supports FlashAttention hardware acceleration and mixture-of-experts feed-forward network computation. Both are important for modern large language model inference workloads.

Meta‘s documentation indicates plans to continue advancing the MTIA roadmap with four new generations of chips within two years. This pace is significantly faster than typical chip development cycles in the industry. The company states this approach enables rapid adaptation to evolving AI techniques while minimizing costs associated with developing and deploying new chip generations.

The goal stated by Meta leadership is creating personal superintelligence for all users, though this remains a long-term aspiration rather than an immediate objective. The current focus remains on scaling infrastructure capacity to support billions of daily users across Facebook, Instagram, WhatsApp, and other platforms while maintaining the lowest possible costs for AI operations.